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SN8P1602b 8-bit micro-controller sonix technology co., ltd version 1.1 SN8P1602b user?s manual general release specification s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improve reliability, function or desig n. sonix does not assume any liability arising out of the application or use of an y product or circuit described her ein; neither does it convey a ny license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems inten ded, for surgical implant into the body, or other applications intended to suppor t or sustain life, or for any other application in which the fai lure of the sonix product could create a situation where personal injury or death may occu r. should buyer purchase or use sonix products for any such uni ntended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subs idiaries, affiliates and distri butors harmless against all claims, cost, damages, and expenses, and re asonable attorney fees arising out of, dire ctly or indirectly, any claim of pers onal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
SN8P1602b 8-bit micro-controller sonix technology co., ltd version 1.1 amendent history version date description ver 1.0 sep. 2003 v1.0 first issue ver 1.1 sep. 2003 1. remove approval sheet 2. remove pcb layout notice section. 3. modify the description of code option notice. 4. add the descripti on of pedge register. 5. modify the descript ion of intrq register. 6. change operating voltage range from ?2.2v ~ 5.5v? to ?2.4v ~ 5.5v? at fosc=3.579545 mhz, ambient temperature = 25 c.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 3 version 1.1 table of content amendent history ............................................................................................................... ................ 2 1 1 1 product overview............................................................................................................... .. 8 general description............................................................................................................ ............... 8 upgrade from SN8P1602/sn8p1603/SN8P1602a............................................................................... 8 features ....................................................................................................................... ............................. 9 selection table................................................................................................................ ..................... 9 system block diagram........................................................................................................... ......... 10 pin assignment ................................................................................................................. .................... 11 pin descriptions ............................................................................................................... ................... 12 pin circuit diagrams ........................................................................................................... ............. 12 2 2 2 code option table .............................................................................................................. .13 SN8P1602b ...................................................................................................................... ............................ 13 3 3 3 address spaces ................................................................................................................. ...... 14 program memory (rom)........................................................................................................... ........ 14 overview ....................................................................................................................... ....................... 14 user reset vector address (0000h) ........................................................................................... 15 interrupt vector address (0008h) ............................................................................................ 15 checksum calculation ........................................................................................................... ...... 17 general purpose program memory area.............................................................................. 18 look-up table description...................................................................................................... .... 18 jump table description......................................................................................................... ........ 20 data memory (ram) .............................................................................................................. ............. 22 overview ....................................................................................................................... ....................... 22 working registers.............................................................................................................. ............... 23 y, z registers ................................................................................................................. ..................... 23
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 4 version 1.1 r registers.................................................................................................................... ....................... 24 program flag ................................................................................................................... .................... 25 reset/wakeup flag .............................................................................................................. ............ 25 carry flag ..................................................................................................................... ...................... 25 decimal carry flag............................................................................................................. ............ 25 zero flag ...................................................................................................................... ....................... 25 accumulator .................................................................................................................... ................... 26 stack operations ............................................................................................................... ................ 27 overview ....................................................................................................................... ....................... 27 stack registers ................................................................................................................ ................. 28 stack operation example........................................................................................................ ..... 29 program counter................................................................................................................ ............... 29 one address skipping ........................................................................................................... .......... 30 multi-address jumping .......................................................................................................... ....... 31 4 4 4 addressing mode................................................................................................................ ... 32 overview....................................................................................................................... .......................... 32 immediate addressing mode...................................................................................................... .32 directly addre ssing mode ....................................................................................................... ... 32 indirectly addressing mode ..................................................................................................... .32 5 5 5 system register ................................................................................................................ .... 33 overview....................................................................................................................... .......................... 33 system register arrangement (bank 0)................................................................................. 33 bytes of system register ....................................................................................................... ......... 33 bits of system register........................................................................................................ ............ 34 6 6 6 power on reset ................................................................................................................. ..... 35 overview....................................................................................................................... .......................... 35 external reset description..................................................................................................... .... 36 low voltage detector (lvd) description ............................................................................ 37
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 5 version 1.1 7 7 7 oscillators .................................................................................................................... ......... 38 overview....................................................................................................................... .......................... 38 clock block diagram ............................................................................................................ ........ 38 oscm register description...................................................................................................... .... 39 external high-speed oscillator .............................................................................................. 40 oscillator mode code option ................................................................................................... 4 0 oscillator devide by 2 code option ....................................................................................... 40 oscillator safe guard code option....................................................................................... 40 system oscillator circuits ..................................................................................................... .... 41 external rc oscillator frequency measurement ................................................................................... .42 internal low-speed oscillator ................................................................................................ 43 system mode description........................................................................................................ ....... 44 overview ....................................................................................................................... ....................... 44 normal mode.................................................................................................................... .................. 44 slow mode ...................................................................................................................... ..................... 44 green mode..................................................................................................................... .................... 44 power down mode ................................................................................................................ ........... 44 system mode control............................................................................................................ .......... 45 system mode switching .......................................................................................................... ....... 46 wakeup time .................................................................................................................... ...................... 47 overview ....................................................................................................................... ....................... 47 hardware wakeup................................................................................................................ ............ 47 external wakeup trigger control ......................................................................................... 48 8 8 8 timers ......................................................................................................................... ................. 49 watchdog timer (wdt)........................................................................................................... .......... 49 timer0 (tc0) ................................................................................................................... .......................... 50 overview ....................................................................................................................... ....................... 50 tc0m mode register ............................................................................................................. ........... 51 tc0c counting register ......................................................................................................... ....... 52 tc0 timer operation sequence .................................................................................................. 5 3
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 6 version 1.1 9 9 9 interrupt...................................................................................................................... ............. 54 overview....................................................................................................................... .......................... 54 inten interrupt enable register .............................................................................................. 55 intrq interrupt request register............................................................................................ 55 interrupt operation description.............................................................................................. 56 gie global interr upt operation............................................................................................... 56 int0 (p0.0) interrupt operation ................................................................................................ .. 57 tc0 interrupt operation ........................................................................................................ ...... 58 multi-interrupt operation ...................................................................................................... ... 59 1 1 1 0 0 0 i/o port ....................................................................................................................... ..... 60 overview....................................................................................................................... .......................... 60 i/o port function table........................................................................................................ ........... 61 i/o port mode.................................................................................................................. ....................... 61 i/o pull up register........................................................................................................... ................. 62 i/o port data register ......................................................................................................... ............ 62 1 1 1 1 1 1 coding issue ................................................................................................................. 63 template code .................................................................................................................. ................... 63 program check list ............................................................................................................. ............. 67 1 1 1 2 2 2 instruction set table........................................................................................... 68 1 1 1 3 3 3 electrical characteristic .............................................................................. 69 absolute maximum rating........................................................................................................ .... 69
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 7 version 1.1 standard electrical characteristic.................................................................................... 69 characteristic graphs .......................................................................................................... ......... 70 1 1 1 4 4 4 package information ........................................................................................... 73 p-dip 18 pin................................................................................................................... ............................. 73 sop 18 pin............................................................................................................................ ....................... 74 ssop 20 pin .................................................................................................................... ............................ 75
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 8 version 1.1 1 1 1 product overview general description the SN8P1602b is an 8-bit micro-contro ller utilized cmos technol ogy and featured with lo w power consumption and high performance by its unique electronic structure. SN8P1602b is designed with the excellent ic structure in cluding the program memory up to 1k-word otp rom, data memory of 48-bytes ram, one 8-bit timer (tc0), a watchd og timer, two interrupt sources (tc0, int0), and 4-level stack buffers. besides, user can choose desired oscillator configuration for th e controller. there are four external oscillator configurations to select for generating system clock, including high/low sp eed crystal, ceramic resonator or cost-saving rc. SN8P1602b also includes an internal rc oscillator for slow mode controlled by programming. upgrade from SN8P1602/sn8p1603/SN8P1602a item SN8P1602b SN8P1602a SN8P1602 sn8p1603 standby current at 3v <1ua 3 ~ 4ua 3 ~ 4ua 70ua pull-up resistor yes yes - - power on reset / brown out reset excellent excellent - good watchdog clock source high clock internal rc high clock internal rc high clock high clock watchdog clock source fixed at internal rc and internal rc clock always enable yes yes - - green mode yes yes - - p0.0 interrupt edge falling/rising/both falling/rising/both falling falling port 1 wakeup level change level change low level low level tc0 event counter yes yes - - external reset recommend value 20k / 0.1uf 20k / 0.33uf 20k / 0.1uf 20k / 0.1uf power on delay at 4mhz ~ 200ms ~ 200ms ~ 70ms ~ 70ms low power code option yes yes - - lvd 1.8v always on 1.8v always on 2.4v on/off 2.4v always on
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 9 version 1.1 features ? memory configuration ? two interrupt sources otp rom size: 1k * 16-bit. one internal interrupt: tc0. ram size: 48 * 8-bit. one external interrupt: int0. ? i/o pin configuration ? four levels stack buffer. input only: p0 bi-directional: p1, p2, ? dual clock system offers four operating modes wakeup: p0, p1 external high clock: rc type up to 10 mhz pull-up resistors: p0, p1, p2 external high clock: crystal type up to 16 mhz external interrupt: p0 internal low clock: rc type 16khz(3v), 32khz(5v) normal mode: both high and low clock active slow mode: low clock only ? on chip watchdog timer. sleep mode: both high and low clock stop ? one 8-bit timer counters. green mode: periodical wakeup by timer. ? package ? 57 powerful instructions four clocks per instruction cycl e p-dip18, sop18, ssop20. all of instructions are one word length. most of instructions are one cycle only. maximum instruction cycle is two. all rom area jmp instruction. all rom area lookup table function (movc) selection table timer pwm wakeup chip rom ram stack tc0 tc1 i/o green mode buzzer pin no. package SN8P1602b 1k*16 48 4 v - 14 v - 6 dip18/sop18 /ssop20
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 10 version 1.1 system block diagram SN8P1602b pc ir rom h-osc timing generator ram system register alu acc interrupt control timer & counter port 0 port 2 port 1 flags internal rc por watch dog pc ir rom h-osc timing generator ram system register alu acc interrupt control timer & counter port 0 port 2 port 1 flags internal rc por watch dog pc ir rom h-osc timing generator ram system register alu acc interrupt control timer & counter port 0 port 2 port 1 flags internal rc por watch dog
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 11 version 1.1 pin assignment otp type: SN8P1602bp (p-dip 18 pins) SN8P1602bs (sop 18 pins) p1.2 1 u 18 p1.1 p1.3 2 17 p1.0 int0/p0.0 3 16 xin rst/vpp 4 15 xout/p1.4 vss 5 14 vdd p2.0 6 13 p2.7 p2.1 7 12 p2.6 p2.2 8 11 p2.5 p2.3 9 10 p2.4 SN8P1602bp SN8P1602bs SN8P1602bx (ssop 20 pins) p1.2 1 u 20 p1.1 p1.3 2 19 p1.0 int0/p0.0 3 18 xin rst/vpp 4 17 xout/p1.4 vss 5 16 vdd vss 6 15 vdd p2.0 7 14 p2.7 p2.1 8 13 p2.6 p2.2 9 12 p2.5 p2.3 10 11 p2.4 SN8P1602bx
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 12 version 1.1 pin descriptions SN8P1602b pad name type description vdd, vss p power supply input pins. place the 0.1f bypass capacitor between the vdd and vss pin. rst/vpp i, p rst: system reset input pin. schmitt tri gger structure, low active, normal stay to ?high?. vpp: otp programming pin. xin i external oscillator input pin. rc mode input pin. xout/p1.4 i/o external oscillator out put pin. in rc mode is p1.4 i/o. p0.0 / int0 i port 0.0 and shared with int0 trig ger pin (schmitt trigger) / built-in pull-up resistors. p1.0 ~ p1.4 i/o port 1.0~port 1.4 bi-d irection pins / built-in pull-up resistors. p2.0 ~ p2.7 i/o port 2.0~port 2.7 bi-d irection pins / built-in pull-up resistors. pin circuit diagrams SN8P1602b note: all of the latch output circuits are push-pull structures. port0 structure pur pur pur pnm, pur pin pnm latch port1~port2 structure pnm pin int. bus port0 structure pur pur pur pnm, pur pin pnm latch port1~port2 structure pnm pin int. bus
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 13 version 1.1 2 2 2 code option table SN8P1602b code option content function description rc low cost rc for external high clock oscillator 32k x?tal low frequency, power saving crystal (e.g. 32.768k) for external high clock oscillator 12m x?tal high speed crystal /resonator (e.g. 12m) for external high clock oscillator high_clk 4m x?tal standard crystal /resonator (e.g. 3.58m) for external high clock oscillator enable external high clock divided by two, fosc = high clock / 2 high_clk / 2 disable fosc = high clock enable enable oscillator safe guard function to enhance noise immunity performance. osg disable disable oscillator safe guard function enable enable watch dog function watch_dog disable disable watch dog function enable enable low power function to save operating current low power disable disable low power function enable enable noise filter function to enhance noise immunity performance noise filter disable disable noise filter function enable enable rom code security function security disable disable rom code security function always_on force watch dog timer clock source come from int 16k rc. a lso int 16k rc never stop both in power down and green mode that means watch dog timer will always enable both in power down and green mode. int_16k_rc by_cpum enable or disable internal 16k (at 3v) rc clock by cpum register table 2-1 SN8P1602b code option table this table is for design guidance, not tested or guarant eed. some values presented are outside specified operating range. this is for information only and devices are guarant eed to operate properly only within the specified range. code option lowest operation voltage enable disable 4 mhz 16 mhz - noise filter/low power/osg 2.2v 2.8v noise filter low power/osg 2.2v 3.5v low power noise filter/osg 2.2v 3.8v osg noise filter/low power 2.2v 2.9v table 2-2 SN8P1602b minimum working voltage vs. code option and clock frequency notice: under high noisy environment, enable ?noise filter ?, ?osg? and disable ?low power? is strongly recommended. the side effect is to increase the minimum working vo ltage if enables ?noise filter?/?osg?/ ?low power? code option. (please refer to characteristic graphs) enable ?low power? option will reduce opera ting current during the normal operating mode. if users select ?32k x?tal? in ?high_clk? opt ion, assembler will force ?osg? to be enabled. if users select ?rc? in ?high_clk? option, assem bler will force ?high_clk / 2? to be enabled.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 14 version 1.1 3 3 3 address spaces program memory (rom) overview the SN8P1602b provides the program memory up to 1024 * 16 -bit to be addressed and is able to fetch instructions through 10-bit wide pc (program counter). it can look up rom data by using rom code registers (r, y, z). 1-word reset vector addresses 1-word interrupt vector addresses 1k words general purpose area 5-word reserved area all of the program memory is partitioned into three coding areas. the first area is located from 00h to 03h(the reset vector area), the second area is a reserved area 04h ~07h, the 3 rd area is for the interrupt vector and the user code area from 0008h to 03feh/0ffeh. the address 08h is the interrupt enter address point. rom 0000h reset vector user reset vector 0001h jump to user start address 0002h jump to user start address 0003h general purpose area jump to user start address 0004h 0005h 0006h 0007h reserved 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . 03feh general purpose area end of user program 03ffh reserved
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 15 version 1.1 user reset vector address (0000h) a 1-word vector address area is used to execute system rese t. after power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h an d all system registers will be set as default values. the following example shows the way to define the reset vector in the program memory. programming tip: defining reset vector chip SN8P1602b org 0 ; 0000h jmp start ; jump to user program address. . ; 0004h ~ 0007h are reserved org 10h start: ; 0010h, the head of user program. . ; user program . . . endp ; end of program interrupt vector address (0008h) a 1-word vector address area is used to execute interr upt request. if any interrupt se rvice executes, the program counter (pc) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. users have to define the interr upt vector. the following example shows the wa y to define the interrupt vector in the program memory. programming tip: defining interrupt vector (example 1) chip SN8P1602b .data pflagbuf .code org 0 ; 0000h jmp start ; jump to user program address. . ; 0004h ~ 0007h are reserved org 8 ; interrupt service routine b0xch a, accbuf ; b0xch doesn?t change c, z flag b0mov a, pflag b0mov pflagbuf, a ; save pflag register in a buffer . . b0mov a, pflagbuf b0mov pflag, a ; restore pflag register from buffer b0xch a, accbuf ; b0xch doesn?t change c, z flag reti ; end of interrupt service routine start: ; the head of user program. . ; user program . jmp start ; end of user program endp ; end of program
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 16 version 1.1 programming tip: defining interrupt vector (example 2) chip SN8P1602b .data pflagbuf .code org 0 ; 0000h jmp start ; jump to user program address. . ; 0001h ~ 0007h are reserved org 08 jmp my_irq ; 0008h, jump to interrupt service routine address org 10h start: ; 0010h, the head of user program. . ; user program . . jmp start ; end of user program my_irq: ;the head of interrupt service routine b0xch a, accbuf ; b0xch doesn?t change c, z flag b0mov a, pflag b0mov pflagbuf, a ; save pflag register in a buffer . . b0mov a, pflagbuf b0mov pflag, a ; restore pflag register from buffer b0xch a, accbuf ; b0xch doesn?t change c, z flag reti ; end of interrupt service routine endp ; end of program remark: it is easy to understand the rules of sonix program from demo programs given above. these points are as following: 1. the address 0000h is a ?jmp? instruction to make the program starts from the beginning. 2. the 0004h~0007h are reserved. users is not allow to use 0004h~0007h addresses. the default value might change from time to time during various production progress. we strongly suggest users do not take this value into the check sum. for detailed information, please check the following checksum calculation section
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 17 version 1.1 checksum calculation the rom addresses 0004h~0007h and last address are reserved area. user shoul d avoid these addresses (0004h~0007h and last address) w hen calculate the checksum value. example: the demo program shows how to avoid 0004h~0007h when calculated checksum from 00h to the end of user?s code mov a,#end_user_code$l b0mov end_addr1,a ;save low end address to end_addr1 mov a,#end_user_code$m b0mov end_addr2,a ;save middle end address to end_addr2 clr y ;set y to 00h clr z ;set z to 00h @@: call yz_check ;call function of check yz value movc ; b0bset fc ;clear c flag add data1,a ;add a to data1 mov a,r adc data2,a ;add r to data2 jmp end_check ;check if the yz address = the end of code aaa: incms z ;z=z+1 jmp @b ;if z!= 00h calculate to next address jmp y_add_1 ;if z=00h increase y end_check: mov a,end_addr1 cmprs a,z ;check if z = low end address jmp aaa ;if not jump to checksum calculate mov a,end_addr2 cmprs a,y ;if yes, check if y = middle end address jmp aaa ;if not jump to checksum calculate jmp checksum_end ;if yes checksum calculated is done. yz_check: ;check if yz=0004h mov a,#04h cmprs a,z ;check if z=04h ret ;if not return to checksum calculate mov a,#00h cmprs a,y ;if yes, check if y=00h ret ;if not return to checksum calculate incms z ;if yes, increase 4 to z incms z incms z incms z ret ;set yz=0008h then return y_add_1: incms y ;increase y nop jmp @b ;jump to checksum calculate checksum_end: ???. ???. end_user_code: ;label of program end
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 18 version 1.1 general purpose prog ram memory area the rom location 0009h~03feh are used as general-purp ose memory. the area is to store both instruction?s op-code and look-up table data. the sn8p 1602b includes jump table function by using program counter (pc) and look-up table function by using rom code registers (r, y, z). the boundary of program memory is s eparated by the high-byte program counter (pch) every 100h. in jump table function and look-up table function, the program coun ter can?t leap over the boundary by program counter automatically. users need to modify the pch value to ?pch+1? when the pcl overflow s (from 0ffh to 000h). look-up table description in the rom?s data lookup function, y register is pointed to the bit 8~bit 15 and z register to the bit 0~bit 7 data of rom address. after movc instruction is executed, the low-byte data will be stored in acc and high-byte data stored in r register. example: to look up the rom data located ?table1?. b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low address. movc ; to lookup data, r = 00h, acc = 35h ; ; increment the index address for next address incms z ; z+1 jmp @f ; not overflow incms y ; z overflow (ffh 00), y=y+1 nop ; ; @@: movc ; to lookup data, r = 51h, acc = 05h. . . ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h ; ? dw 2012h ; ? causion: the y register will not increase automatical ly when z register cros ses boundary from 0xff to 0x00. therefore, user must take care such situation to avoid loop-up table errors. if z register overflows, y register must be added one. the followi ng inc_yz macro shows a simple method to process y and z registers automatically. note: because the program counter (pc) is only 12-bit, the x register is useless in the application. users can omit ?b0mov x, #table1$h?. sonix ice s upports larger program memory addressing capability. please be sure that x register is ?0? to avoid unpredicted error in loop-up table operation. example: inc_yz macro inc_yz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 nop ; not overflow @@: endm
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 19 version 1.1 the other example of loop-up table is to add y or z index r egister by accumulator. please be careful if ?carry? happen. example: increase y and z register by b0add/add instruction b0mov y, #table1$m ; to set lookup table?s middle address. b0mov z, #table1$l ; to set lookup table?s low address. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x0035 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012 . . . . ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h ; ? dw 2012h ; ?
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 20 version 1.1 jump table description the jump table operation is one of multi-address jumpin g function. add low-byte program counter (pcl) and acc value to get one new pcl. the new program counter (pc) points to a series jump instructions as a listing table. it is easy to make a multi-jump program depends on the value of the accumulator (a). when carry flag occurs after ex ecuting of ?add pcl, a?, it will not affect p ch register. users have to check if the jump table crosses over the rom page boundary or the listing file generated by so nix assembly software. we suggest users to place the jump table at the beginning of the program memory page (xx 00h) to avoid errors to occur when editing the program. example : org 0x0100 ; the jump table is from the head of the rom boundary b0add pcl, a ; pcl = pcl + acc, the pch can?t be changed. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point in following example, the jump table starts at 0x00fd. wh en execute b0add pcl, a. if acc = 0 or 1, the jump table points to the right address. if the acc is larger then 1 will cause error because pch doesn't increase one automatically. we can see the pcl = 0 when acc = 2 but the pch still keep in 0. the program counter (pc) will enter the wrong address 0x0000 and the system will be in a unexpected operation mode. it is important to check whether the jump table crosses over the boundary (xxffh to xx00h). a good coding style is to put the jump table at the start of rom boundary (e.g. 0100h). example (incorrect): if the ?jump table? cro sses over rom boundary, the program will cause the errors to occur. rom address . . . . . . 0x00fd b0add pcl, a ; pcl = pcl + ac c, the pch can?t be changed. 0x00fe jmp a0point ; acc = 0 0x00ff jmp a1point ; acc = 1 0x0100 jmp a2point ; acc = 2 jump table cross boundary here 0x0101 jmp a3point ; acc = 3 . . . . sonix provides a macro for safe jump table function. th is macro will check the rom boundary and move the jump table to the right position automatically. the side e ffect of this macro maybe wastes some rom size. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif add pcl, a endm note: ?val? is the number of the jump table listing number.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 21 version 1.1 example: ?@jmp_a? application in sonix macro file called ?macro3.h?. b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point jmp a4point ; acc = 4, jump to a4point if the jump table position is from 00fdh to 0101h, the ?@jmp_ a? macro will make the jump table to start from 0100h.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 22 version 1.1 data memory (ram) overview the SN8P1602b has internally built-in data memory up to 48 bytes for storing the general-purpose data. 48 * 8-bit ram the memory is separated into bank 0. the bank 0 uses t he first 48 bytes as general-purpose area, and the remaining 128 bytes area as system register. SN8P1602b ram location 000h ? ? 000h~02fh/07fh of bank 0 store general-purpose data (48 bytes /128bytes). ? ? ? 02fh general purpose area 080h ? 080h~0ffh of bank 0 store system registers (128 bytes). ? ? ? ? system register bank 0 0ffh end of bank 0 area
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 23 version 1.1 working registers these y,z registers can be used as the general-purpos e working buffer or access rom?s and ram?s data. for instance, all of the rom table can be looked-up by y and z registers. the data of ram memory can be indirectly accessed with y and z registers. y, z registers the y and z registers are the 8-bit buffers. there ar e three major functions of these registers. can be used as general working registers can be used as ram data pointers with @yz register can be used as rom data pointer with t he movc instruction for look-up table 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 example: uses yz register as the data pointer to access data in the ram address 025h of bank0. b0mov y, #00h ; to set ram bank 0 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc example: uses the yz register as data pointer to clear the ram data b0mov y, #0 ; y = 0, bank 0 b0mov z, #07fh ; y = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; z ? 1, if z= 0, finish the routine jmp clr_yz_buf ; not zero clr @yz end_clr: ; end of clear general purpose data memory area of bank 0 .
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 24 version 1.1 r registers r register is an 8-bit buffer. there ar e two major functions of the register. can be used as working register for store high-byte dat a of look-up table (movc instruction executed, the high- byte data of specified rom address will be stored in r register and the low-byte data will be stored in acc). 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 note: please refer to the ?look-up table description? about r regi ster look-up table application.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 25 version 1.1 program flag the pflag includes carry flag (c), decimal carry flag (dc) and zero flag (z). if the result of operating is zero or there is carry, borrow occurrence, then these fl ags will be set to pflag register. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd - - - c dc z read/write r/w r/w - - - r/w r/w r/w after reset - - - - - 0 0 0 reset/wakeup flag nt0 npd description 0 0 during the sleep mode, the devic e wakes up by the watch dog. such function only valid when users set ?int_16k_rc? code option as ?always_on? 0 1 watchdog timer overflow in normal/slow/green mode. 1 0 during the sleep mode, the devic e wakes up by the reset pin. 1 1 external reset or lvd reset active note: watchdog timer can also be used as a fixed-period timer if the watchdog reset function has been disabled. carry flag c = 1: when executed arithmetic addition with overflow or executed arithmetic subtracti on without borrow or executed rotation instruction with logic ?1? shifting out. c = 0: when executed arithmetic additi on without overflow or executed arithmet ic subtraction with borrow or executed rotation instruction with logic ?0? shifting out. decimal carry flag dc = 1: if executed arithmetic addition with overflow of low nibble or executed ar ithmetic subtraction without borrow of low nibble. dc = 0: if executed arithmetic addition wit hout overflow of low nibble or executed arithmetic subtraction with borrow of low nibble. zero flag z = 1: when the content of acc or target memory is ze ro after executing instructions involving a zero flag. z = 0: when the content of acc or target memory is not zero after executing instructions involving a zero flag.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 26 version 1.1 accumulator the acc is an 8-bit data register responsible for trans ferring or manipulating data between alu and data memory. if the result of operating is zero (z) or there is carry (c or dc) occurrence, then these flags will be set to pflag register. acc is not in data memory (ram), so acc can?t be acce ss by ?b0mov? instruction dur ing the instant addressing mode. example: read and write acc value. ; read acc data and store in buf data memory mov buf, a ; write a immediate data into acc mov a, #0fh ; write acc data from buf data memory mov a, buf the system doesn?t store acc and pfla g value when interrupt executed. a cc and pflag data must be saved to other data memories. example: protect acc and working registers. accbuf equ 00h ; accbuf is acc data buffer. pflagbuf equ 01h ; pflagbuf is pflag data buffer. int_service: b0xch a, accbuf ; store acc value b0mov a, pflag ; store pflag value b0mov pflagbuf,a . . . . b0mov a, pflagbuf ; re-load pflag value b0mov pflag,a b0xch a, accbuf ; re-load acc by b0xch command, and which will not affect the pflag again. reti ; exit interrupt service vector note: to save and re-load acc data, users must use ?b0xch? instruction, or else the pflag register might be modified by acc operation.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 27 version 1.1 stack operations overview the stack buffer of SN8P1602b has 4-level. these buffers are designed to push and pop up program counter?s (pc) data when interrupt service routine is exec uted. the stkp register is a pointer designed to point active level in order to push or pop up data from stack buffer. the stknh and stkn l are the stack buffers to store program counter (pc) data. stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp - 1 stkp + 1 call / interrupt ret / reti stkp pch pcl stkp stk0h stk1h stk2h stk3h stk0l stk1l stk2l stk3l stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp = 0 stkp = 1 stkp = 2 stkp = 3 stkp - 1 stkp + 1 call / interrupt ret / reti stkp - 1 stkp + 1 stkp - 1 stkp - 1 stkp + 1 call / interrupt ret / reti stkp stkp pch pcl pch pch pcl pcl stkp stkp stk0h stk1h stk2h stk3h stk0l stk1l stk2l stk3l
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 28 version 1.1 stack registers the stack pointer (stkp) is a 3-bit register to store t he address used to access the st ack buffer, 10-bit data memory (stknh and stknl) set aside for temp orary storage of stack addresses. the two stack operations are writing to the top of the stac k (push) and reading from the top of stack (pop). push operation decrements the stkp and the pop operation increments each time. that makes the stkp always point to the top address of stack buffer and wr ite the last program counter val ue (pc) into the stack buffer. the program counter (pc) value is stored in the stack bu ffer before a call instruction ex ecuted or during interrupt service routine. stack operation is a lifo type (last in and first out). the stack pointer (stkp) and stack buffer (stknh and stknl) are located in t he system register area bank 0. SN8P1602b 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 stkpbn: stack pointer (n = 0 ~ 2) gie: global interrupt control bit. 0 = disable, 1 = enable. please refer to the interrupt chapter. example: stack pointer (stkp) reset, we strongl y recommended to clear the stack pointers in the beginning of the program. mov a, #00000111b b0mov stkp, a SN8P1602b 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - - - - - snpc9 snpc8 read/write - - - - - - r/w r/w after reset - - - - - - 0 0 stkn = (n = 3 ~ 0) SN8P1602b 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 for SN8P1602b : stkn = (n = 3 ~ 0)
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 29 version 1.1 stack operation example the two kinds of stack-save operations re fer to the stack pointer (stkp) and writ e the content of program counter (pc) to the stack buffer are call instructi on and interrupt service. under each conditi on, the stkp decreases and points to the next available stack location. the stack buffer stor es the program counter about the op-code address. the stack-save operation is as the following table. SN8P1602b stkp register stack buffer stack level stkpb2 stkpb1 stkpb0 high byte low byte description 0 1 1 1 free free - 1 1 1 0 stk0h stk0l - 2 1 0 1 stk1h stk1l - 3 1 0 0 stk2h stk2l - 4 0 1 1 stk3h stk3l - > 4 0 1 0 - - stack over, error there are stack-restore operations correspond to each push operation to restore the prog ram counter (pc). the reti instruction uses for interrupt service routine. the ret inst ruction is for call instruction. when a pop operation occurs, the stkp is incremented and points to the next free stack loca tion. the stack buffer restores the last program counter (pc) to the program counter registers. the stac k-restore operation is as the following table. SN8P1602b stkp register stack buffer stack level stkpb2 stkpb1 stkpb0 high byte low byte description 4 0 1 1 stk3h stk3l - 3 1 0 0 stk2h stk2l - 2 1 0 1 stk1h stk1l - 1 1 1 0 stk0h stk0l - 0 1 1 1 free free - program counter the program counter (pc) is a 10-bit binary counter sepa rated into the high-byte 2 and the low-byte 8 bits. this counter is responsible for pointing a location in order to fe tch an instruction for kernel circuit. normally, the program counter is automatically incremented with eac h instruction during program execution. besides, it can be replaced with specific address by execut ing call or jmp instruction. when jmp or call instruction is executed, the desti nation address will be inserted to bit 0 ~ bit 9. SN8P1602b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - - - - - pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset - - - - - - 0 0 0 0 0 0 0 0 0 0 pch pcl
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 30 version 1.1 one address skipping there are nine instructions (cmprs, incs, incms, de cs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these instructions is true, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is true, the pc will add 2 steps to skip next instruction. b0bts1 fc ; to skip, if carry_flag = 1 jmp c0step ; else jump to c0step. . c0step: nop b0mov a, buf0 ; move buf0 value to acc. b0bts0 fz ; to skip, if zero flag = 0. jmp c1step ; else jump to c1step. . c1step: nop if the acc is equal to the immediat e data or memory, the pc will add 2 steps to skip next instruction. cmprs a, #12h ; to skip, if acc = 12h. jmp c0step ; else jump to c0step. . c0step: nop if the destination increased by 1, wh ich results overflow of 0xff to 0x00, the pc will add 2 steps to skip next instruction. incs instruction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. ? c0step: nop incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? c0step: nop if the destination decreased by 1, which results underflo w of 0x00 to 0xff, the pc will add 2 steps to skip next instruction. decs instruction: decs buf0 jmp c0step ; jump to c0step if acc is not zero. ? c0step: nop decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? c0step: nop
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 31 version 1.1 multi-address jumping users can jump around the multi-address by either jmp instruction or add m, an instruction (m = pcl) to activate multi-address jumping function. if carry flag occurs after ex ecution of add pcl, a, the ca rry flag will not affect pch register. example: if pc = 0323h (pch = 03h pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h . . . . ; pc = 0328h . . mov a, #00h b0mov pcl, a ; jump to address 0300h example: if pc = 0323h (pch = 03h pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + ac c, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point . . ;
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 32 version 1.1 4 4 4 addressing mode overview the SN8P1602b provides three addressing modes to acce ss ram data, including immediate addressing mode, directly addressing mode and indirectly address mode. immediate addressing mode the immediate addressing mode uses an imm ediate data to set up the location (? mov a, # i ?, ? b0mov m, # i ?) in acc or specific ram. immediate addressing mode mov a, #12h ; to set an immediate data 12h into acc directly addressing mode the directly addressing mode moves the c ontent of ram location in or out of acc.(? mov a,12h ?, ? mov 12h, a ?). directly addressing mode b0mov a, 12h ; to get a content of location 12h of bank 0 and save in acc indirectly addressing mode the indirectly addressing mode is to access the memory by the data pointer registers (y/z). example: indirectly addressing mode with @yz register clr y ; to clear y register to access ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 33 version 1.1 5 5 5 system register overview the ram area located in 80h~ffh bank 0 is system register area. the main purpose of system registers is to control peripheral hardware of the chip. using system registers c an control i/o ports, timers and counters by programming. the memory map provides an easy and quick reference source for writing application prog ram. these system registers accessing is controlled by the selected memory bank (rban k = 0) or the bank 0 read/write instruction (b0mov, b0bset, b0bclr?). system register arrangement (bank 0) bytes of system register SN8P1602b 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 - - r z y - pflag rpage - - - - - - - - 9 - - - - - - - - - - - - - - - - a - - - - - - - - - - - - - - - - b - - - - - - - - - - - - - - pur pedge c p1w p1m p2m - - - - - intrq inten oscm - - - pcl pch d p0 p1 p2 - - - - - t0m - tc0m tc0c - - - stkp e - - - - - - - @yz - - - - - - - - f - - - - - - - - stk3l stk3h stk2l stk2h stk1l stk1h stk0l stk0h description pflag = rom page and special flag register. r = w orking register and rom look-up data buffer. p1w = port 1 wakeup register. y, z = working, @yz and rom addressing register. pnm = port n input/output mode register. pn = port n data buffer. intrq = interrupt request register. inten = interrupt enable register. oscm = oscillator mode register. pch, pcl = program counter. tcnm = timer n mode register. tcnc = timer n counting register. t0m.1= tc0gn, tc0 green mode wakeup flag. stkp = stack pointer buffer. stk0 ~stk3 = stack 0 ~ stack 3 buffer. @yz = ram yz indirect addressing index pointer.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 34 version 1.1 bits of system register SN8P1602b system register table address bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 r/w remarks 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 086h nt0 npd - - - c dc z r/w pflag 0beh - - - - - pur2 pur1 pur0 w pur 0bfh pedgen - - p00g1 p00g0 - - - w pedge 0c0h 0 0 0 p14w p13w p12w p11w p10w r/w p1w wakeup register 0c1h 0 0 0 p14m p13m p12m p11m p10m r/w p1m i/o direction 0c2h p27m p26m p25m p24m p23m p22m p21m p20m r/w p2m i/o direction 0c8h 0 0 tc0irq 0 0 0 0 p00irq r/w intrq 0c9h 0 0 tc0ien 0 0 0 0 p00ien r/w inten 0cah wtcks wdrst 0 cpum1 cpum0 clkmd stphx 0 r/w oscm 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - - - - - pc9 pc8 r/w pch 0d0h - - - - - - - p00 r p0 data buffer 0d1h - - - p14 p13 p12 p11 p10 r/w p1 data buffer 0d2h p27 p26 p25 p24 p23 p22 p21 p20 r/w p2 data buffer 0d8h - - - - - - tc0gn - r/w t0m 0dah tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks 0 0 0 r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dfh gie - - - - stkpb2 stkpb1 stkpb0 r/w stkp stack pointer 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz index pointer 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3pc3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h - - - - - - s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2 pc3 s2pc2 s2pc1 s2pc0 r/w stk2l 0fbh - - - - - - s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - - - - - s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0 pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - - - - - s0pc9 s0pc8 r/w stk0h note a): to avoid system error, please be sure to put all the ?0? as it indicates in the above table b). all of register names had been declared in sn8asm assembler. c). one-bit name had been declared in sn8asm assembler with ?f? prefix code. d). ?b0bset?, ?b0bclr?, ?bset?, ?bclr? instructio ns are only available to the ?r/w? registers. e). for detail description, please refer to the ?system register quick reference table?
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 35 version 1.1 6 6 6 power on reset overview SN8P1602b provides two system resets. one is external rese t and the other is internal low voltage detector (lvd). the external reset is a simple rc circuit connecting to the reset pi n. the low voltage detector (lvd) is built in internal circuit. when one of the reset devices occurs, the system will rese t and the system registers become initial value. the timing diagram is as the following. vdd external reset internal reset signal end of lvd reset lvd end of external reset lvd detect level external reset detect level SN8P1602b power on reset timing diagram
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 36 version 1.1 external reset description the external reset is a low level active device. the rese t pin receives the low voltage and resets the system. when the voltage detects high level, it stops rese tting the system. users can use an exter nal reset circuit to control system operation. external reset vdd internal reset signal external reset detect level end of external reset system reset users must make sure the vdd is stabl e earlier than external reset. otherwise, the power on reset maybe fail. the external reset circuit is a simple rc circuit as the following figure. gnd vcc rst vdd mcu vss r 20k ohm c 0.1uf
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 37 version 1.1 under different environment, by placing a diode in between vcc and reset pin will help the brownout reset. gnd vcc rst vdd mcu vss r 20k ohm c 0.1uf diode low voltage detector (lvd) description the lvd is a low voltage detector. it detects vdd level and reset the system as the vdd lower than the detected voltage. the detect level is 1.8v. if the v dd lower than 1.8v, the system resets. system reset lvd detect level end of lvd reset vdd lvd
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 38 version 1.1 7 7 7 oscillators overview the SN8P1602b is a dual clock micro-c ontroller system. there are external high-speed clock and internal low-speed clock. the high-speed clock is generated from the external oscillator circuit. the low-speed clock is generated from on-chip rc oscillator circuit. both the external high-speed clock and the internal low-speed clock can be syst em clock (fosc). the system clock is divided by 4 to be the instruction cycle (fcpu). fcpu = fosc / 4 clock block diagram fl cpum0 lxosc. fcpu fosc/4 cpum0 fh hxosc. xin xout stphx hxrc cpum0 divided by 4 clkmd divided by 2 osg divided by 2 1 : disable 0 : enable osg : oscillator safe guard 1 : disable -- system default 0 : enable hxrc(1:0) is code option ?00= rc ?01 =32 khz oscillator ?10 = high speed oscillator (>10mhz) ?11 = standard oscillator (4mhz) fl cpum0 lxosc. fl cpum0 lxosc. fcpu fosc/4 cpum0 fcpu fosc/4 cpum0 fh hxosc. xin xout stphx hxrc cpum0 fh hxosc. xin xout stphx hxrc cpum0 divided by 4 clkmd divided by 4 divided by 4 clkmd divided by 2 divided by 2 osg osg divided by 2 1 : disable 0 : enable osg : oscillator safe guard 1 : disable -- system default 0 : enable hxrc(1:0) is code option ?00= rc ?01 =32 khz oscillator ?10 = high speed oscillator (>10mhz) ?11 = standard oscillator (4mhz) hxosc: external high-speed clock lxosc: internal low-speed clock osg: oscillator safe guard
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 39 version 1.1 oscm register description the oscm register is an oscillator cont rol register. it controls oscillator stat us, system mode, wa tchdog timer clock rate. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst 0 cpum1 cpum0 clkmd stphx 0 read/write r/w r/w - r/w r/w r/w r/w - after reset 0 0 - 0 0 0 0 - stphx: external high-speed oscillator control bit. 0 = free r un, 1 = stop. this bit only controls external high-speed oscillator. if stphx=1, the internal low-speed rc oscillator is still running. clkmd: system high/low clock mode: bit 0 = normal (dual) mode, 1 = slow mode. cpum1, cpum0: cpu operating mode control bit: 00 = normal 01 = sleep (power down) mode 10 = green mode 11 = reserved. wdrst: watchdog timer reset bit 0 = non-reset 1 = clear the watchdog timer?s counter. please refer to the ?watchdog timer chapter? for detailed information. wtcks: watchdog clock source 0 = fcpu 1 = internal rc low clock
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 40 version 1.1 external high-speed oscillator SN8P1602b can be operated in four different oscillator modes. there are external rc oscillator modes, high crystal/resonator mode (12m code option), standard crys tal/resonator mode (4m code option) and low crystal mode (32k code option). for different applicat ion, the users can select one of suit able oscillator mode by programming code option to generate system high-s peed clock source after reset. example: stop external high-speed oscillator b0bset fstphx ; to stop exter nal high-speed oscillator only. example: when entering the power down mode, both external high-speed oscillator and internal low-speed oscillator will be stopped. b0bset fcpum0 ; to stop external high- speed oscillator and in ternal low-speed ; oscillator called powe r down mode (sleep mode). oscillator mode code option SN8P1602b has four oscillator modes for different app lications. these modes are 4m, 12m, 32k and rc. the main purpose is to support different oscillator types and frequencies. mcu needs more current when operating at high-speed mode than the low-speed mode. for crystals, there are three steps to select. if the oscillator is rc type, to select ?rc? and the system will divide the frequency by 2 automatically. user can select oscillator mode from code option table before compiling. following is the code option table. code option oscillator mode remark 00 rc mode output the fcpu square wave from xout pin. 01 32k 32768hz 10 12m 12mhz ~ 16mhz 11 4m 3.58mhz oscillator devide by 2 code option SN8P1602b has a code option to divide ex ternal clock by 2,called ?high_clk / 2?. if ?high_clk / 2? is enabled, the external clock frequency is divided by 8 fo r the fcpu. fcpu is equal to fosc/8. if ?high_clk / 2? is disabled, the fcpu is equal to fosc/4. note: in rc mode, ?high_clk / 2? is always enabled. oscillator safe guard code option SN8P1602b builds in an osc illator safe guard (osg) to make oscillator more stable. it is a low-pass filter circuit and stops high frequency noise into system fr om external oscillator circuit. this func tion makes system to work better under ac noisy conditions.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 41 version 1.1 system oscillator circuits mcu xin vdd xout vss crystal 20pf 20pf crystal/ceramic oscillator mcu xin vdd vss xout c r rc oscillator xin vdd mcu vss xout external clock input external clock input note1: the external oscillator circuit must be directly from vss pin of micro-controller. note2: the input source of xin pin received from externa l oscillator circuit, the c ode option can be either be rc type oscillator or crystal type oscillator. note3: in rc type oscillator code option situation, the external clock frequency is auto matically divided by 2.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 42 version 1.1 external rc oscillator frequency measurement there are two ways to get the fosc frequency of external rc oscillator. one way is to measure the xout output waveform. moreover, the other way is to measure the exte rnal rc frequency by software instruction cycle (fcpu). example: fcpu instruction cy cle of external oscillator b0bset p1m.0 ; set p1.0 to be output mode for outputting fcpu toggle signal. @@: b0bset p1.0 ; output fcpu toggle signal in low-sp eed clock mode. b0bclr p1.0 ; measure the fcpu frequency by oscilloscope. jmp @b note: do not measure the rc frequency directly from xin, the probe impendence will affect the rc value.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 43 version 1.1 internal low-speed oscillator the internal low-speed oscillato r is built in the micro-controller. the low- speed clock source is a rc type oscillator circuit. example: stop internal low-speed oscillator b0bset fcpum0 ; to stop external high- speed oscillator and in ternal low-speed ; oscillator called powe r down mode (sleep mode). note: the internal low-speed clock can?t be turned o ff individually. it is controlled by cpum0 bit of oscm register. the low-speed oscillator uses rc type oscillator circuit. the frequency is affected by the voltage and temperature of the system. in common condition, the fr equency of the rc oscillator is about 16khz at 3v and 32khz at 5v. the relation between the rc frequency and voltage is as the following figure. internal rc vs. vdd 7.329 8.663 11.998 15.333 18.668 22.003 25.338 28.673 32.008 35.343 38.678 0 5 10 15 20 25 30 35 40 1.80 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50 vdd (volts) fintrc (khz) example: measure the internal rc frequency by instruct ion cycle (fcpu). the internal rc frequency is the fcpu multiplied by 4. we can get the fosc frequency of internal rc from the fcpu frequency. b0bset p1m.0 ; set p1.0 to be output mode for outputting fcpu toggle signal. b0bset fclkmd ; switch the system cloc k to internal low-speed clock mode. @@: b0bset p1.0 ; output fcpu toggle signal in low-sp eed clock mode. b0bclr p1.0 ; measure the fcpu frequency by oscilloscope. jmp @b
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 44 version 1.1 system mode description overview the chip is featured with low power consumption by switching around four different modes as following. high-speed mode low-speed mode power-down mode (sleep mode) green mode normal mode in normal mode, the system clock source is external hi gh-speed clock. after power on, the system works under normal mode. the instruction cycle is fosc/4. when the external hi gh-speed oscillator is 3.58mhz, the instruction cycle is 3.58mhz/4 = 895khz. from normal mode, the system can get into power do wn mode, slow mode and green mode. slow mode in slow mode, the system clock source is internal low-speed rc clock. to se t clkmd =1, the system switches into slow mode. in slow mode, the system functions similar to the normal mode except using the internal rc clock. the system in slow mode can switch back to high-speed normal mo de. on the other hand, it can be easily switch to power down mode and green mode for less power consumption. green mode the green mode provides a time-variable wakeup function. us ers can decide wakeup time by setting tc0 timer. there are two paths into green mode. one is from normal mode and the other is from slow mode. in normal mode, the tc0 timer overflow time is very short. in slow mode, the overflow time is longer. users can select appropriate situation for their applications. under green mode, t he power consumption is around 5ua in 3v condition. the system can be waked up to last system mode by tc0 timer timeout and p0 trigger signal. power down mode the power down mode is also called sleep mode. the mcu st ops working as sleeping status. to set cupm0 = 1, the system gets into power down mode. the external high-s peed and low-speed os cillators are turned off. the system can be waked up by p0, p1 trigger signal.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 45 version 1.1 system mode control SN8P1602b type operating mode description mode normal slow green power down (sleep) remark hx osc. running by stphx by stphx stop lx osc. running running running stop cpu instruction executi ng executing stop stop tc0 timer *active *act ive *active inactive * active by program watchdog timer active active by int_16k_rc by int_16k_rc internal interrupt all active all active tc0 all inactive external interrupt all active all active all active all inactive wakeup source - - p0, p1, tc0 reset p0, p1, reset normal mode green mode slow mode power down mode (sleep mode) p0, p1 wake-up function active. external reset circuit active. cpum1, cpum0 = 01 clkmd = 0 clkmd = 1 cpum1, cpum0 = 10 p0, p1 wake-up function active. tc0 time out. p0, p1 wake-up function active. tc0 time out. external reset circuit active. external reset circuit active. normal mode green mode slow mode power down mode (sleep mode) p0, p1 wake-up function active. external reset circuit active. cpum1, cpum0 = 01 clkmd = 0 clkmd = 1 cpum1, cpum0 = 10 p0, p1 wake-up function active. tc0 time out. p0, p1 wake-up function active. tc0 time out. external reset circuit active. external reset circuit active.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 46 version 1.1 system mode switching switch normal/slow mode to power down (sleep) mode. cpum0 = 1 b0bset fcpum0 ; set cpum0 = 1. during the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode. switch normal mode to slow mode. b0bset fclkmd ;to set clkmd = 1, change the system into slow mode b0bset fstphx ;to stop external high -speed oscillator for power saving. switch slow mode to normal mode (the ext ernal high-speed oscillator is still running) b0bclr fclkmd ;to set clkmd = 0 switch slow mode to normal mode ( the external high-speed oscillator stops) if external high clock stop and program want to switch back normal mode. it is necessary to delay at least 10ms for external clock stable. b0bclr fstphx ; turn on the external high-speed oscillator. b0mov z, #27 ; if vdd = 5v, internal rc=32khz (typical) will delay @@: decms z ; 0.125ms x 81 = 10.125ms for external clock stable jmp @b ; b0bclr fclkmd ; change the system back to the normal mode example: go into green mode and enable tc0 wakeup function. ; set tc0 timer wakeup function. b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0enb ; to disable tc0 timer mov a,#20h ; b0mov tc0m,a ; to set tc0 clock = fcpu / 64 mov a,#74h b0mov tc0c,a ; to set tc0c initial value = 74h (to set tc0 interval = 10 ms) b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0irq ; to clear tc0 interrupt request b0bset ftc0enb ; to enable tc0 timer b0bset ftc0gn ; to enable tc0 wakeup function ; go into green mode b0bclr fcpum0 ;to set cpumx = 10 b0bset fcpum1 note: if tc0enb = 0 or tc0gn = 0, tc0 will not be ab le to wakeup from green mode to normal/slow mode function.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 47 version 1.1 wakeup time overview the external high-speed oscillator needs a delay time from stopping to operating. the delay is necessary for oscillator to be stabilized.. the delay time for external high-speed osc illator restart is someti mes called wakeup time. following are two conditions require wakeup time, one is swit ching power down mode to normal mode, and the other is switching slow mode to normal mode. for the first conditi on, SN8P1602b provides 2048 oscillator clocks as the wakeup time. the second condition, users need to take the wakeup time into consideration, which involved stabilizing period for start up the exter nal high-speed oscillator. hardware wakeup when the system is in power down mode (sleep mode), the external high-speed oscillator stops. when waked up from power down mode, mcu waits for 2048 exter nal high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. after the wakeup time, the system goes into the normal mode. the value of the wakeup time is as the following. the wakeup time = 1/fosc * 2048 (sec) + x?tal settling time the x?tal settling time is depended on the x?tal type. typically, it is about 2~4ms. example: in power down mode (sleep mode), the syst em is waked up by p0 or p1 trigger signal. after the wakeup time, the system goes into normal mode. the wakeup time of p0, p1 wakeup function is as the following. the wakeup time = 1/fosc * 2048 = 0.57 ms (fosc = 3.58mhz) the total wakeup time = 0.57ms + x?tal settling time under power down mode (sleep mode), only the i/o ports wi th wakeup function are able to wake the system up to normal mode. the port 0 and port 1 have wakeup function. po rt 0 wakeup function always enables, but the port 1 is controlled by the p1w register. SN8P1602b 0c0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w 0 0 0 p14w p13w p12w p11w p10w read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 p10w~p14w: port 1 wakeup function c ontrol bits. 0 = none wakeup function, 1 = enable each pin of port 1 wakeup function.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 48 version 1.1 external wakeup trigger control in the SN8P1602b, the wakeup trigger direction is control by pedge register. pedge initial value = 0xx0 0xxx 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge pedgen - - p00g1 p00g0 - - - r/w - - r/w r/w - - - bit7 pedgen: interrupt and wakeup trigger edge control bit. 0 = disable edge trigger function. port 0: low-level wakeup trigger and falling edge interrupt trigger. port 1: low-level wakeup trigger. 1 = enable edge trigger function. p0.0: wakeup and interrupt trigger is controlled by p00g1 and p00g0 bits. port 1: level change (falling or rising edge) wakeup trigger. bit[4:3] p00g[1:0]: port 0.0 edge select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 49 version 1.1 8 8 8 timers watchdog timer (wdt) the watchdog timer (wdt) is a binary up counter designed for monitoring program execution. if the program goes into the unknown status by noise interferen ce, wdt overflow signal raises and resets mcu. the instruction that clears the watchdog timer (? b0bset fwdrst ?) s hould be executed within a certain per iod. if an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst 0 cpum1 cpum0 clkmd stphx 0 read/write r/w r/w - r/w r/w r/w r/w - after reset 0 0 - 0 0 0 0 - wdrst: watchdog timer reset bit. 0 = non reset, 1 = clear the watchdog timer counter. wtcks: watchdog clock source select bit 0 = fcpu, 1 = internal rc low clock. watchdog timer overflow table. wtcks clkmd code option watchdog timer overflow time 0 0 4m_x?tal / 12m_x?tal / rc 1 / ( fcpu 2 14 16 ) = 293 ms, fosc=3.58mhz 0 0 32k_x?tal 1 / ( fcpu 2 8 16 ) = 500 ms, fosc=32768hz 0 1 - 1 / ( fcpu 2 14 16 ) = 65.5s, fosc=16khz@3v 1 - - 1 / ( 16k 512 16 ) ~ 0.5s @3v - - enable int_16k_rc 1 / ( 16k 512 16 ) ~ 0.5s @3v note: the watchdog timer can be enabled or disabled by the code option. if disabled, the watchdog timer can also be served as fixed-period timer by checking the nt0 flag. example: an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: b0bset fwdrst ; clear the watchdog timer counter. . . call sub1 call sub2 . . . . . . jmp main
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 50 version 1.1 timer0 (tc0) overview the tc0 is an 8-bit binary up timer and event counter, using tc0m register to select tc0c?s clock source from gtmr or from external int0 pin ( falling edge trigger) for counti ng a precision time. if tc0 timer occurs an overflow (from ffh to 00h), it will continue counting and issue a time-out signal to trigger tc0 interrupt to request interrupt service. the main purposes of the tc0 timer is as following. 8-bit programmable timer: generates interrupts at specific time intervals based on the selected clock frequency. external event counter: counts system ?events? based on falling edge detection of external clock signals at the int0 input pin. 2 (8 -tc0rate ) fcpu tc0enb tc0c 8-bit binary counter tc0 time out pre_load int 0 (schmitter t rigger) tc0cks internal data bus cp um1,0 2 (8 -tc0rate ) fcpu tc0enb tc0c 8-bit binary counter tc0 time out pre_load int 0 (schmitter t rigger) tc0cks internal data bus cp um1,0
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 51 version 1.1 tc0m mode register the tc0m is an 8-bit read/write timer mode register. by l oading different value into the tc0m register, users can modify the timer period as program executing. eight rates for tc0 timer can be selected by tc0rate0 ~ tc 0rate2 bits. the range is from fcpu/2 to fcpu/256. the tc0m initial value is zero and the rate is fcpu/256. the bit7 of tc0m called tc0enb is the control bit to start tc0 timer. the combination of these bits is to determine the tc0 timer clock frequency and the intervals. 0dah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks 0 0 0 read/write r/w r/w r/w r/w r/w - - - after reset 0 0 0 0 0 - - - tc0enb: tc0 counter enable bit. ?0? = disable, ?1? = enable. tc0rate2~tc0rate0: tc0 internal clock select bits . 000 = fcpu/256, 001 = fcpu/128, ? , 110 = fcpu/4, 111 = fcpu/2. tc0cks: tc0 clock source select bit. 0 = fcpu, 1 = external clock comes from int0/p0.0 pin. note1: the ice s8kc does not support the pwm0out and tc0out function. the pwm0out and tc0out must use the s8kd ice (or later) to verify the function. note2: when tc0cks=1, tc0 became an external event counter. no more p0.0 interrupt request will be raised. (p0.0irq will be always 0)
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 52 version 1.1 tc0c counting register tc0c is an 8-bit counter register for the timer (tc0). tc0c must be reset whenever the tc0enb is set to ?1? to start the timer. tc0c is incremented each time a clock puls e of the frequency determined by tc0rate0 ~ tc0rate2. when tc0c has incremented to ?0ffh?, it counts to ?00h? an overflow generated . under tc0 interrupt service request (tc0ien) enable condition, the tc0 interrupt request flag will be set to ?1? and the system executes the interrupt service routine. the tc0c has no auto re load function. after tc0c overflow, the tc0c is continuing counting. users need to redefine the tc0c value to get an accurate time. 0dbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the basic timer table interval time of tc0 high speed mode (fcpu = 3.58mhz / 4) low speed mode (fcpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms the equation of tc0c initial value is as following. tc0c initial value = 256 - (tc0 interrupt interval time * input clock) example: to set 10ms interval time for tc0 interr upt at 3.58mhz high-speed mode. tc0c value (74h) = 256 - (10ms * fcpu/64) tc0c initial value = 256 - (tc0 inte rrupt interval time * input clock) = 256 - (10ms * 3.58 * 10 6 / 4 / 64) = 256 - (10 -2 * 3.58 * 10 6 / 4 / 64) = 116 = 74h
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 53 version 1.1 tc0 timer operation sequence the tc0 timer?s sequence of operation may be as following. set the tc0c initial value to setup the interval time. set the tc0enb to be ?1? to enable tc0 timer. tc0c is incremented by one after each clock pulse corresponding to tc0m selection. tc0c overflow if tc0c from ffh to 00h. when tc0c overflow occur, the tc0irq flag is set to be ?1? by hardware. execute the interrupt service routine. users reset the tc0c value and resume the tc0 timer operation. example: setup the tc0m and tc0c. b0bclr ftc0ien ; to disable tc0 interrupt service b0bclr ftc0enb ; to disable tc0 timer mov a,#20h ; b0mov tc0m,a ; to set tc0 clock = fcpu / 64 mov a,#74h ; to set tc0c initial value = 74h b0mov tc0c,a ;(to set tc0 interval = 10 ms) b0bset ftc0ien ; to enable tc0 interrupt service b0bclr ftc0irq ; to clear tc0 interrupt request b0bset ftc0enb ; to enable tc0 timer example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; b0xch inst ruction do not change c,z flag b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a,#74h ; reload tc0c b0mov tc0c,a . . ; tc0 interrupt service routine . . jmp exit_int ; end of tc0 interrupt service routine and exit interrupt vector . . . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 54 version 1.1 9 9 9 interrupt overview the SN8P1602b provides 2 interrupt sour ces, including 1 internal interrupt (tc0) and 1 external interrupt (int0). the external interrupt can wakeup the chip while the system is switched from power down mode to high-speed normal mode. once interrupt service is execut ed, the gie bit in stkp register will clear to ?0? for stopping other interrupt request. on the contrast, when in terrupt service exits, the gie bit will set to ?1? to accept the next interrupts? request. all of the interrupt request signals are stored in intrq register. SN8P1602b note: the gie bit must enable during all interrupt operation. intrq 2-bit latchs tc0irq interrupt enable gating global interrupt request signal interrupt vector address (0008h) tc0 time out inten interrupt enable register the interrupt trigger edge : int0 = falling edge p00irq int0 trigger intrq 2-bit latchs tc0irq interrupt enable gating global interrupt request signal interrupt vector address (0008h) tc0 time out inten interrupt enable register the interrupt trigger edge : int0 = falling edge p00irq int0 trigger
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 55 version 1.1 inten interrupt enable register inten is the interrupt request control register including one internal interrupts, one exte rnal interrupts enable control bits. one of the register to be set ?1? is to enable the interrupt request function. once of the interrupt occur, the stack is incremented and program jump to org 8 to execute interrupt service routines. t he program exits the interrupt service routine when the returning interrupt service routine instruction (reti) is executed. SN8P1602b 0c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten 0 0 tc0ien 0 0 0 0 p00ien read/write - - r/w - - - - r/w after reset - - 0 - - - - 0 p00ien : external p0.0 interrupt control bit. 0 = disable, 1 = enable. tc0ien : timer 0 interrupt control bit 0 = disable, 1 = enable. intrq interrupt request register intrq is the interrupt request flag register. the register incl udes all interrupt request indication flags. each one of the interrupt requests occurs, the bit of the intrq register would be set ?1?. the intrq value needs to be clear by programming after detecting the flag. in the interrupt vect or of program, users know the any interrupt requests occurring by the register and do the routi ne corresponding of the interrupt request. SN8P1602b 0c8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq 0 0 tc0irq 0 0 0 0 p00irq read/write - - r/w - - - - r/w after reset - - 0 - - - - 0 p00irq : external p0.0 interrupt request bit. 0 = non-request, 1 = request. tc0irq : tc0 timer interrupt request controls bit 0 = non request, 1 = request. when interrupt occurs, the related request bit of intrq r egister will be set to ?1? no matter the related enable bit of inten register is enabled or disabled. if the related bit of in ten = 1 and the related bit of intrq is also set to be ?1?. as the result, the system will execute the interrupt vector (org 8). if the re lated bit of inten = 0, moreover, the system won?t execute interrupt vector even when the related bit of intrq is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 56 version 1.1 interrupt operation description gie global interrupt operation gie is the global interrupt control bit. all interrupts start work after the gie = 1. it is necessary for interrupt service request. one of the interrupt requests occurs, and the program co unter (pc) points to the interrupt vector (org 8) and the stack add 1 level. SN8P1602b 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 gie: global interrupt control bit. 0 = disable, 1 = enable. example: set global interrupt control bit (gie). b0bset fgie ; enable gie note: the gie bit must enable during all interrupt operation.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 57 version 1.1 int0 (p0.0) interrupt operation the p0.0 interrupt trigger direction is control by pedge register. pedge initial value = 0xx0 0xxx 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge pedgen - - p00g1 p00g0 - - - r/w - - r/w r/w - - - bit7 pedgen: interrupt and wakeup trigger edge control bit. 0 = disable edge trigger function. port 0: low-level wakeup trigger and falling edge interrupt trigger. port 1: low-level wakeup trigger. 1 = enable edge trigger function. p0.0: wakeup and interrupt trigger is controlled by p00g1 and p00g0 bits. port 1: level change (falling or rising edge) wakeup trigger. bit[4:3] p00g[1:0]: port 0.0 edge select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction. example: int0 interrupt request setup. b0bset fp00ien ; enable int0 interrupt service b0bclr fp00irq ; clear int0 interrupt request flag b0bset fgie ; enable gie example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq . . ; int0 interrupt service routine . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector when the int0 trigger occurs, the p00irq will be set to ?1 ? no matter the p00ien is enable or disable. if the p00ien = 1 and the trigger event p00irq is also set to be ?1?. as t he result, the system will execute the interrupt vector (org 8). if the p00ien = 0 and the trigger event p00irq is still se t to be ?1?. moreover, the sy stem won?t execute interrupt vector even when the p00irq is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 58 version 1.1 tc0 interrupt operation example: tc0 interrupt request setup. b0bclr ftc0ien ; disable tc0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = fcpu / 64 mov a, #74h ; set tc0c initial value = 74h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc0ien ; enable tc0 interrupt service b0bclr ftc0irq ; clear tc0 interrupt request flag b0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0xch a, accbuf ; store acc value. b0mov a, pflag b0mov pflagbuf, a b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, #74h b0mov tc0c, a ; reset tc0c. . . ; tc0 interrupt service routine . . exit_int: b0mov a, pflagbuf b0mov pflag, a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector when the tc0c counter overflows, the tc0irq will be set to ?1? no matter the tc0ien is enable or disable. if the tc0ien and the trigger event tc0irq is set to be ?1?. as t he result, the system will execute the interrupt vector. if the tc0ien = 0, the trigger event tc0irq is still set to be ?1?. moreover, the system won?t execute interrupt vector even when the tc0ien is set to be ?1?. users need to be cautio us with the operation under multi-interrupt situation.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 59 version 1.1 multi-interrupt operation under certain condition, the software designer uses more than one interrupt requests. processing multi-interrupt request requires setting the priority of the interrupt requests. the irq flags of interrupts are controlled by the interrupt event. nevertheless, the irq flag ?1? does n?t mean the system will execute the interrupt vector. and which means the irq flags can be set ?1? by the events wi thout enable the interrupt. once the ev ent occurs, the irq will be logic ?1?. the irq and its trigger event relationship is as the below table. interrupt name trigger event description p00irq p0.0 trigger controlled by pedge tc0irq tc0c overflow for multi-interrupt conditions, two things need to be taking care of. one is to set the priority for these interrupt requests. two is using ien and irq flags to decide which interrupt to be executed. users have to check interrupt control bit and interrupt request flag in interrupt routine. example: check the interrupt request under multi-interrupt operation org 8 ; interrupt vector b0xch a, accbuf ; store acc value. b0mov a, pflag ; store pflag value b0mov pflagbuf,a intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp inttc0chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 ; jump to int0 interrupt service routine inttc0chk: ; check tc0 interrupt request b0bts1 ftc0ien ; check tc0ien jmp int_exit ; jump to exit of irq b0bts0 ftc0irq ; check tc0irq jmp inttc0 ; jump to tc0 interrupt service routine int_exit: b0mov a, pflagbuf ; restore pflag value b0mov pflag,a b0xch a, accbuf ; restore acc value. reti ; exit interrupt vector
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 60 version 1.1 1 1 1 0 0 0 i/o port overview the SN8P1602b provides 3 ports for users? application, consisting one input only port (p0) and two i/o ports (p1, p2,). each port consists input pull-up resistors. the direction of i/o port can be selected by pnm register. when the system resets, these ports will then be set as input port without pull up resistors. the pull-up resistor can be set up by pur register. SN8P1602b note: all of the latch output circuits are push-pull structures. . port0 structure pur pur pur pnm, pur pin pnm latch port1~port2 structure pnm pin int. bus port0 structure pur pur pur pnm, pur pin pnm latch port1~port2 structure pnm pin int. bus
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 61 version 1.1 i/o port function table SN8P1602b port/pin i/o function description remark general-purpose input function external interrupt (int0) see p0.0 i wakeup from power down mode see general-purpose input/output function p1.0~p1.4 i/o wakeup from power down mode level change p2.0~p2.7 i/o general-purpose input/output function note: the p1.4 enables when the external oscillator is rc type. i/o port mode the port direction is programmed by pnm register. port 0 is always input mode. port 1 and port 2 can select input or output direction. SN8P1602b 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m 0 0 0 p14m p13m p12m p11m p10m read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 SN8P1602b 0c2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2m p27m p26m p25m p24m p23m p22m p21m p20m read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 when pnm=0, the pn is input mode pnm=1, the pn is output mode users can program them by bit cont rol instructions (b0bset, b0bclr). example: i/o mode selecting clr p1m ; set all ports to be input mode. clr p2m mov a, #0ffh ; set all ports to be output mode. b0mov p1m, a b0mov p2m, a b0bclr p1m.2 ; set p1.2 to be input mode. b0bset p1m.2 ; set p1.2 to be output mode.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 62 version 1.1 i/o pull up register SN8P1602b 0beh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pur - - - - - pur2 pur1 pur0 read/write - - - - - w w w after reset - - - - - 0 0 0 example: i/o pull up register clr pur ; disable all ports pull-up register. mov a, #07h ; enable port0, 1, 2 pull-up register, b0mov pur, a ; i/o port data register SN8P1602b 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - - - - - - - p00 read/write - - - - - - - r after reset - - - - - - - 0 SN8P1602b 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 - - - p14 p13 p12 p11 p10 read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 SN8P1602b 0d2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 p27 p26 p25 p24 p23 p22 p21 p20 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 example: read data from input port. b0mov a, p0 ; read data from port 0 b0mov a, p1 ; read data from port 1 b0mov a, p2 ; read data from port 2 example: write data to output port. mov a, #55h ; write data 55h to port 1 and port 2 b0mov p1, a b0mov p2, a example: write one bit data to output port. b0bset p1.3 ; set p1.3 and p2.5 to be ?1?. b0bset p2.5 b0bclr p1.3 ; set p1.3 and p2.5 to be ?0?. b0bclr p2.5 example: port bit test. b0bts1 p0.0 ; bit test 1 for p0.0 b0bts0 p1.2 ; bit test 0 for p1.2
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 63 version 1.1 1 1 1 1 1 1 coding issue template code ;******************************************************************************* ; filename : template.asm ; author : sonix ; purpose : template code for sn8x16xx ; revision : 09/01/2002 v1.0 first issue ;******************************************************************************* ;* (c) copyright 2002, sonix technology co., ltd. ;******************************************************************************* chip SN8P1602b ; select the chip ;------------------------------------------------------------------------------- ; include files ;------------------------------------------------------------------------------- .nolist ; do not list the macro file includestd macro1.h includestd macro2.h includestd macro3.h .list ; enable the listing function ;------------------------------------------------------------------------------- ; constants definition ;------------------------------------------------------------------------------- ; one equ 1 ;------------------------------------------------------------------------------- ; variables definition ;------------------------------------------------------------------------------- .data org 0h ;data section start from ram address 0 wk00 ds 1 ;temporary buffer for main loop iwk00 ds 1 ;temporary buffer for isr accbuf ds 1 ;accumulator buffer pflagbuf ds 1 ;pflag buffer ;------------------------------------------------------------------------------- ; bit variables definition ;------------------------------------------------------------------------------- wk00b0 equ wk00.0 ;bit 0 of wk00 iwk00b1 equ iwk00.1 ;bit 1 of iwk00
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 64 version 1.1 ;------------------------------------------------------------------------------- ; code section ;------------------------------------------------------------------------------- .code org 0 ;code section start jmp reset ;reset vector ;address 4 to 7 are reserved org 8 jmp isr ;interrupt vector org 10h ;------------------------------------------------------------------------------- ; program reset section ;------------------------------------------------------------------------------- reset: mov a,#07fh ;initial stack pointer and b0mov stkp,a ;disable global interrupt b0mov pflag,#00h ;pflag = x,x,x,x,x,c,dc,z mov a,#40h ;clear watchdog timer and initial system mode b0mov oscm,a call clrram ;clear ram call sysinit ;system initial b0bset fgie ;enable global interrupt ;------------------------------------------------------------------------------- ; main routine ;------------------------------------------------------------------------------- main: b0bset fwdrst ;clear watchdog timer call mnapp jmp main ;------------------------------------------------------------------------------- ; main application ;------------------------------------------------------------------------------- mnapp: ; put your main program here ret ;----------------------------------- ; jump table routine ;----------------------------------- org 0x0100 ;the jump table should start from the head ;of boundary. b0mov a,wk00 and a,#3 add pcl,a jmp jmpsub0 jmp jmpsub1 jmp jmpsub2 ;-----------------------------------
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 65 version 1.1 jmpsub0: ; subroutine 1 jmp jmpexit jmpsub1: ; subroutine 2 jmp jmpexit jmpsub2: ; subroutine 3 jmp jmpexit jmpexit: ret ;return main ;------------------------------------------------------------------------------- ; isr (interrupt service routine) ; arguments : ; returns : ; reg change: ;------------------------------------------------------------------------------- isr: ;----------------------------------- ; save acc ;----------------------------------- b0xch a,accbuf ;b0xch instruction do not change c,z flag b0mov a,pflag b0mov pflagbuf,a ;----------------------------------- ; interrupt service routine ;----------------------------------- b0bts0 fp00irq jmp int0isr b0bts0 ftc0irq jmp tc0isr ;----------------------------------- ; exit interrupt service routine ;----------------------------------- isrexit: b0mov a, pflagbuf b0mov pflag, a ;restore the pflag b0xch a,accbuf ;restore the reg. a ;b0xch instruction do not change c,z flag reti ;exit the interrupt routine
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 66 version 1.1 ;------------------------------------------------------------------------------- ; int0 interrupt service routine ;------------------------------------------------------------------------------- int0isr: b0bclr fp00irq ;process p0.0 external interrupt here jmp isrexit ;------------------------------------------------------------------------------- ; tc0 interrupt service routine ;------------------------------------------------------------------------------- tc0isr: b0bclr ftc0irq ;process tc0 interrupt here jmp isrexit ;------------------------------------------------------------------------------- ; sysinit ; system initial to define register, ram, i/o, timer...... ;------------------------------------------------------------------------------- sysinit: ret ;------------------------------------------------------------------------------- ; clrram ; use index @yz to clear ram (00h~2fh) ;------------------------------------------------------------------------------- clrram: clr y ; b0mov z,#0x2f ;set @yz address from 2fh clrram10: clr @yz ;clear @yz content decms z ;z = z ? 1 , skip next if z=0 jmp clrram10 clr @yz ;clear address $00 ret ;------------------------------------------------------------------------------- endp
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 67 version 1.1 program check list item description undefined bits a ll bits those are marked as ?0? (undefined bits) in system registers should be set ?0? to avoid unpredicted system errors. interrupt do not enable interrupt before initializing ram. non-used i/o non-used i/o ports should be set as output low mode or pull-up at input mode to save current consumption. sleep mode enable on-chip pull-up resistors of port 0 and port 1 to avoid unpredicted wakeup. stack buffer be careful of function call and interrupt serv ice routine operation. don?t let stack buffer overflow or underflow. system initial 1. write 0x7f into stkp register to initial stack pointer and disable global interrupt 2. clear all ram. 3. initialize all system regist er even unused registers. noisy immunity 1. enable osg and high_clk / 2 code option together 2. enable noise filter code option in SN8P1602b. 3. enable the watchdog option to protect system crash. 4. non-used i/o ports should be set as output low mode 5. constantly refresh importan t system registers and variabl es in ram to avoid system crash by a high electrical fast transient noise. 6. disable low power function
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 68 version 1.1 1 1 1 2 2 2 instruction set table field mnemonic description c dc z cycle mov a,m a m - - 1 m mov m,a m a - - - 1 o b0mov a,m a m (bank 0) - - 1 v b0mov m,a m (bank 0) a - - - 1 e mov a,i a i - - - 1 b0mov m,i m i, (m = only for working registers r, y, z , rbank & pflag) - - - 1 xch a,m a m - - - 1 b0xch a,m a m (bank 0) - - - 1 movc r, a rom [y,z] - - - 2 adc a,m a a + m + c, if occur carry, then c=1, else c=0 1 a adc m,a m a + m + c, if occur carry, then c=1, else c=0 1 r add a,m a a + m, if occur carry, then c=1, else c=0 1 i add m,a m a + m, if occur carry, then c=1, else c=0 1 t b0add m,a m (bank 0) m (bank 0) + a, if occur carry, then c=1, else c=0 1 h add a,i a a + i, if occur carry, then c=1, else c=0 1 m sbc a,m a a - m - /c, if occur borrow, then c=0, else c=1 1 e sbc m,a m a - m - /c, if occur borrow, then c=0, else c=1 1 t sub a,m a a - m, if occur borrow, then c=0, else c=1 1 i sub m,a m a - m, if occur borrow, then c=0, else c=1 1 c sub a,i a a - i, if occur borrow, then c=0, else c=1 1 daa to adjust acc?s data format from hex to dec. - - 1 and a,m a a and m - - 1 l and m,a m a and m - - 1 o and a,i a a and i - - 1 g or a,m a a or m - - 1 i or m,a m a or m - - 1 c or a,i a a or i - - 1 xor a,m a a xor m - - 1 xor m,a m a xor m - - 1 xor a,i a a xor i - - 1 swap m a (b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 r rrc m a rrc m - - 1 o rrcm m m rrc m - - 1 c rlc m a rlc m - - 1 e rlcm m m rlc m - - 1 s clr m m 0 - - - 1 s bclr m.b m.b 0 - - - 1 bset m.b m.b 1 - - - 1 b0bclr m.b m(bank 0).b 0 - - - 1 b0bset m.b m(bank 0).b 1 - - - 1 cmprs a,i zf,c a - i, if a = i, then skip next instruction - 1 + s b cmprs a,m zf,c a ? m, if a = m, then skip next instruction - 1 + s r incs m a m + 1, if a = 0, then skip next instruction - - - 1 + s a incms m m m + 1, if m = 0, then skip next instruction - - - 1 + s n decs m a m - 1, if a = 0, then skip next instruction - - - 1 + s c decms m m m - 1, if m = 0, then skip next instruction - - - 1 + s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m(bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m(bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 rompages1/0, pc13~pc0 d - - - 2 call d stack pc15~pc0, pc15/14 rompages1/0, pc13~pc0 d - - - 2 m ret pc stack - - - 2 i reti pc stack, and to enable global interrupt - - - 2 s retlw pc stack, and to load a value by pc+a - - - 2 c nop no operation - - - 1 note: any instruction that read/write from oscm, will add an extra cycle.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 69 version 1.1 1 1 1 3 3 3 electrical characteristic absolute maximum rating (all of the voltages referenced to vss) supply voltage (vdd)????????????????????????????????????? - 0.3v ~ 6.0v input in voltage (vin)?????????????????? ??????????????..vss - 0.2v ~ vdd + 0.2v operating ambient temperature (top)????????????????????????????..-20 c ~ + 70 c storage ambient temperature (tstor)?????????????????????????????-30 c ~ + 125 c power consumption (pc)??????????????????????????????????????500 mw standard electrical characteristic SN8P1602b (all of voltages referenced to vss, vdd = 5.0v, fosc = 3.579545 mhz, ambient temperature is 25 c unless otherwise notice.) parameter sym. description min. typ. max. unit normal mode (osg, low power disable) 2.4 5.0 5.5 v normal mode (osg enable, low power disable) 2.4 5.0 5.5 v normal mode (osg disable, low power enable) 2.9 5.0 5.5 v normal mode (osg, low power enable) 2.9 5.0 5.5 v operating voltage vdd programming mode, vpp = 12.5v 4.5 5.0 5.5 v ram data retention voltage vdr - 1.5 - v vil1 all input pins except those specified below vss - 0.3vdd v vil2 input with schmitt trigger buffer - port0 vss - 0.2vdd v vil3 reset pin ; xin ( in rc mode ) vss - 0.3vdd v input low voltage vil4 xin ( in x?tal mode ) vss - 0.3vdd v vih1 all input pins except thos e specified below 0.7vdd - vdd v vih2 input with schmitt trigger buffer ?port0 0.8vdd - vdd v vih3 reset pin ; xin ( in rc mode ) 0.9vdd - vdd v input high voltage vih4 xin ( in x?tal mode ) 0.7vdd - vdd v reset pin leakage current ilekg vin = vdd - - 1 ua i/o port input leakage current ilekg pull-up resistor disable, vin = vdd - - 2 ua port1 output source current ioh vop = vdd ? 0.5v - 12 - sink current iol vop = vss + 0.5v - 15 - ma port2 output source current ioh vop = vdd ? 0.5v - 12 - sink current iol vop = vss + 0.5v - 15 - ma intn trigger pulse width tint0 int0 ~ int2 interrupt request pulse width 2/fcpu - - cycle crystal type or ceramic resonator 32768 4m 16m vdd = 3v, rc type for external mode - 6m - oscillator frequency fhosc vdd = 5v, rc type for external mode - 10m - hz vdd= 5v 4mhz - 3 8 ma vdd= 3v 4mhz - 1 2 ma idd1 run mode (low power disable) vdd= 3v 32768hz - 50 100 ua vdd= 5v 4mhz - 2 5 ma idd2 run mode (low power enable) vdd= 3v 4mhz - 0.8 2 ma vdd= 5v 32khz int. rc - 25 50 ua idd3 slow mode (stop high clock) vdd= 3v 16khz int. rc - 7 20 ua vdd= 5v - 1 2 ua idd4 sleep mode vdd= 3v - 0.6 1 ua vdd= 5v 32khz int. rc - 15 30 supply current idd5 green mode (stop high clock) vdd= 3v 16khz int. rc 3 10 ua lvd detect voltage vdet low voltage detect level - 1.8 - v note: date in typical (typ.) column is base on characterization results at 25 j . this data is design for guidance only and is not tested.
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 70 version 1.1 characteristic graphs the graphs in this section are for design guidance, not te sted or guaranteed. in some graphs, the data presented are outside specified operating range. this is for informat ion only and devices are guaranteed to operate properly only within the specified range. SN8P1602b figure 13-1working voltage vs. frequency figure 13-2 working voltage vs. frequency (osg, low power, noise filter disable) (noise filter enable, osg, low power disable) figure 13-3 working voltage vs. frequency figure 13-4 working voltage vs. frequency (low power enable, osg, noise filter disable) (osg enable, noise filter, low power disable) figure 13-5 typical stop mode current (idd4) vs. vdd figure 13-6 typical slow mode current (idd3) vs. vdd (stop high clock) 0.0 0.5 1.0 1.5 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 vdd ua 0 5 10 15 20 25 30 2.0 2.5 3.0 3.5 4.0 4.5 5.0 vdd ua working area 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2 4 8 12 16 20 fosc mhz vdd working area 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 248121620 fosc mhz vdd working area 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2 4 8 12 16 20 fosc mhz vdd working area 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 248121620 fosc mhz vdd
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 71 version 1.1 figure 13-7 typical run mode current (idd1) vs. fosc figure 13-8 typical run mode current (idd2) vs. fosc (low power disable) (low power enable) figure 13-9 typical green mode current vs. fosc figure 13-10 typical green mode current vs. vdd (without stopping high clock) (stop high clock) figure 13-11 typical ioh vs. vdd figure 13-12 typical iol vs. vdd 0 2 4 6 8 10 2 6 10 14 18 fos c mhz ma 3v 5v 0 2 4 6 8 10 2 6 10 14 18 fos c mhz ma 3v 5v 0.0 1.0 2.0 3.0 4.0 2 6 10 14 18 fos c mhz ma 3v 5v 0 2 4 6 8 10 12 14 16 2.0 2.5 3.0 3.5 4.0 4.5 5.0 vdd ua -14 -12 -10 -8 -6 -4 -2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 vdd ma 0 2 4 6 8 10 12 14 16 2.0 2.5 3.0 3.5 4.0 4.5 5.0 vdd ma
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 72 version 1.1 figure 13-13 typical slow mode frequency vs. vdd 0 5 10 15 20 25 30 2.0 2.5 3.0 3.5 4.0 4.5 5.0 vdd fos c khz
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 73 version 1.1 1 1 1 4 4 4 package information p-dip 18 pin min nor max min nor max symbols (inch) (mm) a - - 0.210 - - 5.334 a1 0.015 - - 0.381 - - a2 0.125 0.130 0.135 3.175 3.302 3.429 d 0.880 0.900 0.920 22.352 22.860 23.368 e 0.300 7.620 e1 0.245 0.250 0.255 6.223 6.350 6.477 l 0.115 0.130 0.150 2.921 3.302 3.810 p b 0.335 0.355 0.375 8.509 9.017 9.525 0 7 15 0 7 15
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 74 version 1.1 sop 18 pin min nor max min nor max symbols (inch) (mm) a 0.093 0.099 0.104 2.362 2.502 2.642 a1 0.004 0.008 0.012 0.102 0.203 0.305 d 0.447 0.455 0.463 11.354 11.557 11.760 e 0.291 0.295 0.299 7.391 7.493 7.595 h 0.394 0.407 0.419 10.008 10.325 10.643 l 0.016 0.033 0.050 0.406 0.838 1.270 0 4 8 0 4 8
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 75 version 1.1 ssop 20 pin min nor max min nor max symbols (inch) (mm) a 0.053 0.063 0.069 1.350 1.600 1.750 a1 0.004 0.006 0.010 0.100 0.150 0.250 a2 - - 0.059 - - 1.500 b 0.008 0.010 0.012 0.200 0.254 0.300 c 0.007 0.008 0.010 0.180 0.203 0.250 d 0.337 0.341 0.344 8.560 8.660 8.740 e 0.228 0.236 0.244 5.800 6.000 6.200 e1 0.150 0.154 0.157 3.800 3.900 4.000 [e] 0.025 0.635 h 0.010 0.017 0.020 0.250 0.420 0.500 l 0.016 0.025 0.050 0.400 0.635 1.270 l1 0.039 0.041 0.043 1.000 1.050 1.100 zd 0.059 1.500 y - - 0.004 - - 0.100 0 - 8 0 - 8
SN8P1602b 8-bit micro-controller sonix technology co., ltd page 76 version 1.1 sonix reserves the right to make change without further notic e to any products herein to im prove reliability, function or design. sonix does not assume any liability arising out of th e application or use of any product or circuit described herein; neither does it convey any license under its patent rights no r the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other applicati on in which the failure of the sonix product could create a situation where personal injury or death may occur. s hould buyer purchase or use sonix products for any such unintended or unauthorized application. buye r shall indemnify and hold sonix and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cos t, damages, and expenses, and reasonabl e attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 9f, no. 8, hsien cheng 5th s t, chupei city, hsinchu, taiwan r.o.c. tel: 886-3-551 0520 fax: 886-3-551 0523 taipei office: address: 15f-2, no. 171, song ted road, taipei, taiwan r.o.c. tel: 886-2-2759 1980 fax: 886-2-2759 8180 hong kong office: address: flat 3 9/f energy plaza 92 gr anville road, tsimshatsui east kowloon. tel: 852-2723 8086 fax: 852-2723 9179 technical support by email: sn8fae@sonix.com.tw

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